Simple CPU design in Verilog -


i trying use wire variable hold output of other module , provide input module. while trying change value test bench, showing error described below.
tb.v:39: error: not valid l-value in tb.
tb.v:4: error: declared here wire. 1 error(s) during elaboration.

note : tb.v name of test bench file.

can tell me, doing wrong?

use testbench control when module2 input driven module1 output or testbench.

reg tb_in, tb_drive; wire out1; wire in2 = (tb_drive) ? tb_in : out1; mod1 mod1 (out1); mod2 mod2 (in2);

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