vhdl - Quartus II use file only in simulation -

i want run simulation in quartus. assign testbench in assignment menu. testbench includes dut(d) , component(e), simulation (so component includes statements not syntesizeable). simulation runs if remove e testbench, when want include e in testbench, error modelsim:

 my_testbench.vhd(197): (vcom-1195) cannot find expanded name "mylib.only_for_simulation". 

how make quartus/modelsim compile e file?

when start simulation, quartus analyzes all files specified in project settings (accessible via menu assignment -> settings -> files). but, elaborates only entities required dut starting top-level entity (see menu assignment -> settings -> general). example, in test project top specifies entity of dut, , my_testbench , only_for_simulation required simulation only. output quartus in messages window after starting simulation:

info (12021): found 2 design units, including 1 entities, in source file my_testbench.vhdl

info (12021): found 2 design units, including 1 entities, in source file top.vhdl

info (12021): found 2 design units, including 1 entities, in source file only_for_simulation.vhdl

info (12127): elaborating entity "top" top level hierarchy

only files store entities found during elaboration added automatically script start modelsim simulator. thus, doesn't matter if my_testbench , only_for_simulation listed project files. further simulation files must always specified in test-bench setup accessible via menu assignment -> settings -> simulation -> compile test bench -> test benches -> new/edit. there, have list files storing my_testbench , only_for_simulation. , have list them in right compilation order, is, only_for_simulation before my_testbench. within dialog, can set library of only_for_simulation mylib via properties. here, screenshot of test-bench setup.

the generated modelsim script stored in sub-directory simulation/modelsim in file extension .do. lists files compiled modelsim. , modelsim compiles them in given order only.