Nonblocking simultaneous assignments to wires and registers in Verilog -

i interested write verilog module simultaneously update several outputs following code, makes 3 operations @ same time (clk 10):

module mymodule (a,b,c,d,e); input a; input b; output c; output d; output e;  wire b; wire a; wire c; wire d;  reg e;  initial begin c <=  #10  (a+b); d <=  #10  a; e  <= #10  b; end  endmodule 

is code legal?

how todo 1 off assign of variables after 10 timeunits or clocks:

as testbench level construct:

reg c,d,e; initial begin   #10;   c = a+b;   d = a;   e = b; end 

for rtl (synthesis) first need testbench clock.
generate clock in testharness :

reg clk ; //rising edge every 10 timesteps initial begin   clk = 0;   #5;    forever begin     #5 ;     clk = ~clk;   end end 

build counter counts 10 , once reaches 10 enables flip-flop load new values.

wire enable = (counter == 4'b10); @(posedge clk or negedge rst_n) begin   if (~rst_n) begin     c <= 1'b0;     d <= 1'b0;     e <= 1'b0;   end   else if (enable) begin     c <=  (a+b);     d <=   a;     e <=   b;     end   end endmodule 

extra verilog tips
outputs implicitly wires no need redefine them.

non-blocking assignments <= use in @(posedge clk) when inferring flip-flops.

regs or logic types can assigned inside always or initial blocks. wires used assign or connectivity between ports.